1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, which is formed with a bipolar transistor being constituted by including a base, an emitter, and a collector on a semiconductor substrate.
2. Description of the Related Art
In recent years, a Bi-CMOS transistor which makes use of characteristics of both a bipolar transistor and a CMOS transistor is rapidly developed. As a requirement for the development of the Bi-CMOS transistors, enhancement of the treatment speed of the devices is cited.
In order to meet the above-described requirement, for example, in an NPN transistor that is part of the Bi-CMOS transistor, a method of increasing operation frequency of the devices by forming a P+ diffusion region to be narrow and reducing a distance between N+ diffusion regions, is known. However, as a result of forming the P+ diffusion region to be narrow, the resistance inside the device is increased, and power consumption is increased.
With respect to the above problem, the resistance can be reduced by increasing the concentration of an impurity which is added to the P+ diffusion region, but a harmful effect such as a leak current can occur by increasing the concentration of the impurity. Consequently, a semiconductor film is conventionally formed on the P+ diffusion region, and the semiconductor film is electrically connected to an emitter electrode and a base electrode, respectively, whereby occurrence of a leak current, diffusion of an impurity, and the like are prevented.
Here, a conventional example of a manufacturing method of the Bi-CMOS transistor will be explained. A multilayer film is formed on a silicon semiconductor substrate, and an opening is formed in the multilayer film on the P+ diffusion region functioning as a base, and on the N+ diffusion region functioning as an emitter. Then, after the semiconductor film is formed on an entire surface, an inside of the opening is masked with a resist, and isotropic plasma etching for the semiconductor film is performed, whereby the semiconductor film is formed only in the opening. The semiconductor film and the base electrode are electrically connected to each other at a side wall part of the opening, and the semiconductor film and the emitter electrode are electrically connected at a bottom part of the opening.
However, the semiconductor film, which is used here, is constituted by at least two kinds of semiconductor elements, and as shown in FIG. 8, the content of Si is higher in its upper layer region and lower layer region, while the content of the other semiconductor element is higher in an intermediate layer region. The above-described respective semiconductor elements are different in the etching rate for the isotropic plasma etching. As compared with Si which mainly composes the upper layer region and the lower layer region of the compound semiconductor film, the semiconductor element which mainly composes the intermediate layer region generally has a higher etching rate, and therefore the semiconductor film after the isotropic plasma etching treatment is in a state with so-called “voids”, in which clearances occur in the intermediate layer region. Accordingly, electrical connection of the base electrode, the P+ diffusion region and the base electrode is hindered, thus naturally making it impossible to meet the transistor property which is initially expected.